CPU632

Features:

New Instruction Capabilities

• AVX - Advanced Vector Extensions increase parallelism for scientific and 3D apps using heavy floating point calculations
• FMA4 and XOP – Floating-Point Vector Multiply-Accumulate and eXtended Operations improves throughput and performance on many integer and floating point vector functions
• AES - Advanced Encryption Standard increases performance on encryption apps like TrueCrypt and PCMark

• The industry's first and only native 8-core desktop processor for unmatched multitasking and pure core performance with "Bulldozer" architecture.
• New 32 nanometer die shrink designed to reduce leakage for improved efficiency, increased clock rate headroom and better thermals.

• Shared L3 cache ( up to 8MB)
• Improved scheduling and pre-fetch capabilities
• 64-ways (16-ways/sub-cache)
• Increased data queue sizes
• Coherency for 8-cores

• Shared FP Scheduler
• Dual 128-bit Floating point engines – capable of teaming together for 256-bit AVX instructions or operating separately with each core

• One 16-bit link at up to 5600MT/s
• Up to 8.0GB/s HyperTransport I/O bandwidth; Up to 16GB/s in HyperTransport Generation 3.0 mode
• Up to 37GB/s total delivered processor-to-system bandwidth (HyperTransport bus + memory bus)
• Benefit: Quick access times to system I/O for better performance.

• A high-bandwidth, low-latency integrated memory controller
• Supports up to DDR3-1866
• Supports new low voltage memories of 1.35V and 1.2V
• Up to 29.9GB/s memory bandwidth for DDR3
• New Pre-Fetcher improvements
• Direct communications to each core in Dual-Core module (APIC registers in each core)
• Benefit: Optimized memory controller to feed more cores.

AMD Virtualization (AMD-V ) Technology with IOMMU

• Silicon feature-set enhancements designed to improve the performance, reliability and security of existing and future virtualization environments by allowing virtualized applications with direct and rapid access to their allocated memory.
• IOMMU is an extension to AMD64 architecture to support address translation and access protection on DMA transfers
• Security for User Level application and Virtual Machine guest operating system
• Address translation and access control
• Device isolation
• Device assignment in virtualized systems
• Security and trusted boot support
• Unified interrupt management

• Enhanced power management features which automatically and instantaneously adjusts performance states and features based on processor performance requirements
• C6 power state flushes the cache and removes voltage from individual cores to help reduce power consumption
• CC6 power state puts all cores in C6 into an even lower power state
• for quieter operation and reduced power requirements
• Separate memory controller power control
• IO-based c-state interface
• Works automatically without the need for drivers or BIOS enablement.
• Power can be switched on or off within a single clock cycle, saving energy with minimal impact to performance